EDN

Logic 101 – Part 2 – Positive vs Negative Logic

1. Logical versus arithmetic views of a digital function. Having said this, it is generally preferable to employ a single consistent format to cover both cases, and it is easier to view logical ...
EDN

Models for high-voltage transistors in a standard CMOS process

Designers of electronics and communications systems are constantly faced with the challenge of integrating greater functionality on less silicon area. Many of the system blocks – such as power ...
CIOL

How does logic chip/memory chip work?

Transistor is a solid state, three terminal semiconductor amplifying device. Transistor is the fundamental component of most electronic circuits. Bipolar, and Field Effect Transistor (FET) are two ...
Electronics Weekly

Updated: X-FAB adds to low-noise transistor portfolio

X-FAB has added three new low-noise transistors to its 180nm process node: a 1.8 V low-noise NMOS, a 3.3 V low-noise NMOS and a 3.3 V low-noise PMOS – all of which offer drastically reduced flicker ...
Electronic Design

Dirt Cheap ASIC Design for Dummies (Part 3): NMOS, PMOS Silicon Design Using a Web Browser

Quickly learn what the difference is between PMOS and NMOS transistors in their structure and operation, and how CMOS works with the two in combination. Siliwiz, a free, browser-based, ASIC layout ...
Semiconductor Engineering

The History Of CMOS

Since CMOS has been around for about 50 years, a comprehensive history would be a book. This blog focuses on what I consider the major transitions. Before CMOS, there was NMOS (also PMOS, but I have ...