Design-Reuse

Renesas Technology Develops Technique that Overcomes Effects of Threshold Variation to Stabilize the Operation of Embedded SRAM built with 65nm Process

High yield achieved for the world's smallest level 6-transistor SRAM memory-cell area (0.494µm 2) ; stabilization technique addresses variability of transistor characteristics. Tokyo, June 15, 2006 −− ...
EDN

Silicon7’s 8-Mbit SRAM sports single-transistor cell

TOKYO — Fabless startup Silicon7 Inc. said it has developed a one-transistor SRAM chip that can replace today's six-transistor SRAMs. The chip combines Silicon7's CompactCell SRAM (CCSRAM) technology ...
Ars Technica

4T SRAM, 6T SRAM, EDRAM, DRAM, and 1T-SRAM for CPUs

These are various forms of local, on-chip memory. Except for the DRAM. 4T (4 transistor) SRAM takes up 4 times the space that regular DRAM does 1T-SRAM seems to be a hybrid of DRAM that allows for ...
Design-Reuse

Renesas Technology Develops Promising Technology for Implementing On-Chip SOI SRAM of 32-Nanometer Generation and Beyond

Tokyo, June 12, 2007 −− Renesas Technology Corp. today announced the development of a technology that is effective in implementing SRAM in processes of the 32 nm (nanometer) generation and beyond, for ...
EDN

Renesas memory cell mixes SRAM, DRAM tech

Tokyo – Renesas Technology Corp. has developed a new SRAM memory cell structure that combines SRAM and DRAM technologies. The device is about half the size of a conventional SRAM cell, but still has ...